During the manufacture of an integrated circuit device (also known as a semiconductor chip), a package is created which encapsulates the integrated circuit. Although ceramic packages are available, packages are commonly formed of a plastic material, such as epoxy. In order to establish connections to each input/output terminal of the encapsulated chip, a lead frame is also formed and at least partially encapsulated within the package. By wire bonding each input/output terminal of the semiconductor chip to the lead frame prior to encapsulation, each input/output terminal of the semiconductor chip can be electrically contacted following encapsulation by establishing appropriate connections with the portion of the lead frame that extends outside the package. The lead frame can have a variety of shapes depending upon the density and integration of the semiconductor chip and the method of mounting the resulting integrated circuit device to a printed circuit board (PCB).
A lead frame connects the encapsulated semiconductor chip to the PCB. As shown in FIG. 1, a lead frame has two main parts, namely, a die pad unit 1 to which the semiconductor chip is attached or mounted, and a plurality of leads 2 concentrated around the die pad unit 1 and extending outwardly from the die pad unit 1. Each lead 2 includes an inner lead 21 which is wire bonded to an input/output terminal of the semiconductor chip and an outer lead 22 which is connected to the PCB. The input/output terminals of the semiconductor chip are connected through wire bonding to respective inner leads 21 of the lead frame prior to encapsulating the semiconductor chip in a plastic or ceramic package. For a plastic package, a plastic material is typically injection molded about the semiconductor chip mounted to the die pad unit 1 and the inner leads 21. As such, the inner leads 21 are frequently covered with epoxy resin during the molding process.
During construction of the lead frame, the die pad unit 1 and the inner leads 21 are generally partially plated with silver (Ag) for increasing their conductivity. Also, the outer leads 22 are typically plated with solder (Sn/Pb) after the epoxy molding process so as to permit more efficient soldering. When plating the outer leads with the solder, however, the solder commonly penetrates the package of the inner leads 21. Accordingly, an additional, typically wet process step must be performed to eliminate the solder that has penetrated to the inner leads 21. Since a wet process is executed after the epoxy molding process, the reliability of the resulting integrated circuit will generally decrease.
In attempt to solve these deficiencies with conventional lead frame construction techniques, a preplated frame (PPF) method was developed. In the PPF method, a plating layer having excellent solder wettability is deposited on the lead frame prior to encapsulating the semiconductor chip and a portion of the lead frame in a package. In a general PPF method, a layer of palladium (Pd) or palladium alloy is deposited on the lead frame. However, since palladium is a precious metal, the general PPF method raises the price of the lead frame. Also, a galvanic coupling phenomenon occurs between the palladium and iron alloy materials from which the lead frame is constructed. Because of the galvanic coupling phenomenon the lead frame will continue to develop corrosion products.
In a further attempt to overcome these shortcomings, a palladium PPF method was developed. In the palladium PPF method, the base metal of the lead frame is plated with a plurality of layers, as described below.
FIGS. 2A-2C are schematic cross-sectional, views of a lead frame plated according to various palladium PPF methods. As shown in FIG. 2A, the lead frame includes a base metal such as copper, a layer of nickel on the base metal, a layer of palladium nickel alloy on the nickel layer, and a layer of palladium on the palladium-nickel alloy. See Japanese Patent Laid - Open Publication Sho 63-2358. As shown in FIG. 2B, the lead frame includes a base metal, a layer of palladium-nickel alloy on the nickel strike layer, a layer of nickel on the palladium nickel alloy layer, and a layer of palladium on the nickel layer. See European Patent Application No. 0 250 146 and European Patent Application No. 0 335 608. As shown in FIG. 2C, a lead frame includes a base metal, a layer of nickel on the base metal, a layer of gold (Au) strike on the nickel layer, a layer of palladium-nickel alloy on the gold strike layer, a layer of palladium on the palladium nickel alloy layer, and a layer of gold on the palladium layer. See U.S. Pat. No. 5,350,991. Unfortunately, none of these palladium PPF methods completely overcome the corrosion problem.
Yet another process for fabricating a lead frame is the two color plating method. In the two color plating method, the outer leads of the lead frame are plated with solder (Sn/Pb) during the process of fabricating the lead frame and prior to encapsulating the semiconductor chip and a portion of the lead frame in the package. The two color plating method increases the reliability of the resulting packaged integrated circuit device since the wet processing step is omitted, thereby also decreasing the price of the lead frame.
FIG. 3 is a phase diagram of solder for plating a lead frame according to conventional techniques. As shown in FIG. 3, the eutectic temperature of the solder (Sn/Pb) is about 183.degree. C. which is much less than the temperatures required during encapsulation of the semiconductor chip in the package. For example, encapsulation techniques commonly require temperatures of over 250.degree. C. which will deleteriously affect the solder.